1. Field of the Invention
The present invention relates to an arithmetic circuit in which an arithmetic unit and a memory are integrated.
2. Description of the Related Art
The configuration called logic-in-memory has been studied to obtain a circuit in which no information is lost even if the power is turned off and to obtain a circuit in which data transfer to separate RAM chips is not required, by constituting a logic circuit with a non-volatile device.
For example, a floating gate type MOS transistor, ferroelectric device, TMR device and the like are proposed as the non-volatile device used in the logic-in-memory (refer to Non-patent literatures 1 to 4, for example).
The logic-in-memory is the one in which an arithmetic unit and a memory which are arranged separately in current circuits are integrated. By integrating the arithmetic unit and the memory, the bottleneck of performance caused by wiring delay which is a problem in the current integrated circuit can be solved.
Further, though the circuit becomes typically large if the arithmetic function is dispersed and given to the memory, if the device including the non-volatile memory function is used, the compact and high performance circuit may be obtained.
The reason why the compact and high performance circuit is obtained is explained in the followings.
A typical digital circuit uses a configuration called a static circuit, specifically, a configuration that uses a bistable flip-flop such as a SRAM basic circuit as a memory circuit.
Because this circuit is bistable, it is suitable for high-speed operation and has a merit such that the static power consumption is low.
However, it is not suitable for high density integration because six elements constitute one bit memory.
On the other hand, if a configuration called a dynamic circuit, specifically, a configuration that uses a DRAM basic circuit as a memory circuit is employed, since two elements constitute one bit memory, there is such a merit that the circuit is suitable for high density integration.
However, because this circuit is monostable and the destructive reading is performed, pre-charging is needed for rewriting (refreshing) and for small signal amplification, which is inconvenient for the high speed operation and also which makes consuming current increase.
Thus, because the high speed operation can not be performed without refreshing processing and the like, the dynamic circuit is not typically used.
Then, if a device having the non-volatile memory function is introduced into a memory circuit, a logic circuit using the above-described dynamic circuit obtained with a fewer elements can be used without the restriction of operation, because the pre-charging for the rewriting (refreshing) and small signal amplification is not needed.
In this way, the compact and high performance logic circuit may be obtained.
Next, the configuration and operation principle of the logic circuit using this dynamic circuit are explained.
In the logic circuit using a dynamic circuit, a configuration called the FPG (Functional Pass Gate) is employed as a circuit that performs the logical operation. This FPG has a configuration including: an arithmetic element, a memory element and a pass gate transistor, where the memory data for the logical operation is stored in the memory element, and the arithmetic element performs the logical operation using this memory data, and then, the result of the logical operation by the arithmetic element is input to a gate of the pass gate transistor, and consequently the pass gate transistor is made to turn on or off in accordance with the result of operation.
In the dynamic circuit, a pass gate transistor of the FPG is connected to match lines, for example, a pre-charging transistor is provided between a match line on the side of one terminal of the pass gate transistor and a power supply voltage, and a evaluation transistor is provided between a match line on the side of the other terminal of the pass gate transistor and a ground potential. Furthermore, a pre-charging line is connected to each gate of the pre-charging transistor and evaluation transistor such that only either of the pre-charging transistor and evaluation transistor is turned on by the pre-charging line (refer to FIG. 2 and FIG. 4 of Non-patent literature 4, for example).
The operations of the FPG are mainly classified into the writing operation and the arithmetic and readout operation.
In the writing operation, for example, the electric voltage or electric current for the writing is applied to the memory element and the memory data is written.
In the arithmetic and readout operation, a process of pre-charging the match line and a process of performing the arithmetic operation of the external input and the memory data are executed in order. Specifically, first, the pre-charging transistor is turned on and the match line is pre-charged with the electric charge. Then, the pre-charge transistor is turned off and the arithmetic operation is executed. At this time, whether or not the electric charge pre-charged in the match line is passed to the ground potential through the pass gate transistor and evaluation transistor is changed in accordance with the result of the arithmetic operation, therefore by this event, an output is determined by 1 or 0.
In addition, because the output is retained until the start of the next pre-charging, the FPG has a function of latching the output.
Further, if the FPG is connected in series, the AND (logical multiply) operation is performed, and if the FPG is connected in parallel, the OR (logical add) operation is performed; therefore, also the logical operation between the results of operation is performed without difficulties.
Next, the logic-in-memory using various non-volatile devices is briefly explained. First, the case that uses a ferroelectric memory (FeRAM) element is explained as an example of the logic-in-memory using the non-volatile device (refer to Non-patent literature 1).
The ferroelectric device called MFS (Metal Ferroelectric Semiconductor) FET is used as the ferroelectric memory element. This MFSFET is formed of three layers of an electrode, ferroelectric thin film and semiconductor and has a structure in which the ferroelectric thin film replaces an SiO2 layer in the typical MOSFET (MOS Field Effect Transistor).
Then, when a voltage V that exceeds a certain voltage Vc is applied from the outside, the relationship between the voltage V and the polarization P inside the ferroelectric has the hysteresis in the ferroelectric. Therefore, a threshold voltage Vth of the MFSFET is changed under the condition of remnant polarization of the ferroelectric.
Accordingly, the threshold voltage changed in accordance with the condition of remnant polarization can be made to correspond to 1 and 0 of the memory data.
In the case where the MFSFET is used as the memory element, the following advantages are obtained:
(1) writing voltage is low and is about ±6V, in comparison with the floating gate MOS transistor used as the flash memory and the like;
(2) memory data can be read out without destruction; and
(3) high speed writing is possible, because the change of polarization in the ferroelectric is performed at a high speed.
The arithmetic circuit that performs operation of the input data and memory data may be formed with this MFSFET.
Specifically, for example, a terminal A of the MFSFET is connected to the ground potential, and the other terminal B thereof is connected to the match line (potential Vm), and a pre-charging transistor is connected to the other terminal B to constitute the above-described FPG. (refer to Non-patent literature 1)
Further, with the input data s=1, 0 being assigned to the MFSFET gate potential Vg and the memory data b=1, 0 being assigned to the MFSFET threshold voltage Vth, the switching characteristic f(s, b) of the FPG may be defined as follows:
f(s, b)=1 (A and B are connected)
f(s, b)=0 (A and B are not connected).
This shows that if the match line potential Vm has fallen to the ground potential (GND), f(s, b)=1 and other than that, f(s, b)=0.
When with respect to two kinds of threshold voltages Vth0 and Vth1, Vth1>Vth0 is obtained, three kinds of gate voltages Vg0, Vg1 and Vg2 are defined such that Vg2>Vth1>Vg1>Vth0>Vg0.
At this time, if the Vg0 and Vg1 are assigned to b=0 and b=1 respectively, f(s, b)=1 is obtained only when s=1 and b=0, and so the result is f(s, b)=s&−b, thus the logical multiply of s and −b is obtained. On the other hand, if the Vg1 and Vg2 are assigned to b=0 and b=1 respectively, f(s, b)=0 is obtained only when s=0 and b=1, and so the result is f(s, b)=s|−b, thus the logical add of s and −b is obtained.
As described above, if three values of the gate voltage are provided corresponding to the 1/O of the input data s, the OR/AND operation with the memory data b can be performed.
Furthermore, a matching search circuit called a CAM (Content Addressable Memory) that is one of the associative memories can be configured.
An EXOR operation is used to detect the matching by bit, and this EXOR operation can be executed, by connecting in parallel two FPGs which compute the logical multiply. A structure is arranged in which two FPGs are connected in parallel for one word and are combined such that the output becomes “0” if any one does not match, and consequently the matching search circuit can be obtained.
Further, by forming the circuit with the MFSFET as described above, for example, a 16 bits matching search circuit can be obtained with 64 pieces of transistor in the dynamic circuit based on the MFSFET, whereas 160 pieces of transistor are required in the static circuit based on the SRAM (refer to Non-patent literature 1).
Next, the logic-in-memory that uses a ferroelectric capacitor as the non-volatile devices is explained (refer to Non-patent literature 2 and Non-patent literature 3).
The ferroelectric capacitor has a structure in which a ferroelectric thin layer replaces an insulation layer of a typical capacitor, and the polarization occurs when the different voltages are applied to both ends of the ferroelectric capacitor. Further, the condition of remnant polarization of the ferroelectric capacitor is determined by the condition of remnant polarization before applying the voltage and difference in potential at the time of applying the voltage.
Then, the voltages Vy1 and Vy2 that are applied to the both ends of the ferroelectric capacitor are assigned to two input data y1 and y2 and the condition of remnant polarization is assigned to the memory data S and so, the result of operation yielded by the two input data y1 and y2 can be retained as the condition of remnant polarization. This result of operation is also preserved even if the power is turned off.
At this time, the operation between the two input data y1 and y2 changes to the AND (logical multiply) operation or the OR (logical add) operation in accordance with the condition of remnant polarization, specifically the memory data s.
Further, the AND operation and the OR operation that are between the external input data y1 or y2 and the memory data s can also be performed.
Therefore, the logical operation function and the memory function can simultaneously be obtained when using the ferroelectric capacitor.
Further, the ferroelectric capacitor and the pass gate transistor are connected to constitute above-described FPG.
Moreover, a basic circuit formed of a logic gate and a memory of a typical CMOS static circuit can be obtained with only one piece of FPG, when including a dynamic circuit which turns on and off this FPG. For example, the logical operation and latch circuit can be obtained with only 5 pieces of transistor, whereas 14 pieces of transistor is required if the CMOS static circuit is used (refer to Non-patent literature 3).
As described above, if the logic circuit is configured using the dynamic circuit formed of a ferroelectric capacitor, the logic circuit can be made small in comparison with the logic circuit configured using the static CMOS circuit having the same function.
Next, as the last example of the logic-in-memory using the non-volatile device, the one that uses a TMR (Tunnel MagnetoResistance effect) element used for a MRAM (Magnetoresistive Random Access Memory) and the like, is explained (refer to Non-patent literature 4).
The TMR element has a structure in which three layers of a ferromagnetic layer (magnetization-free layer) where the direction of magnetization is changed by the outside magnetic field, an extremely thin insulation layer and a ferromagnetic layer (magnetization-fixed layer) where the direction of magnetization is fixed without depending on the outside magnetic field are stacked.
This TMR element has a characteristic that the electrical resistance increases and decreases in accordance with the change in the direction of magnetization of the magnetization-free layer due to the outside magnetic field. In other words, the resistance becomes low when the directions of the magnetization-free layer and the magnetization-fixed layer are parallel and the resistance becomes high when the directions of the magnetization-free layer and the magnetization-fixed layer are anti-parallel.
Therefore, the resistance of this TRM element can be stored as memory data.
In order to operate the TMR element as the memory element, the writing wiring is arranged for each TMR element in parallel to the easy-magnetization axis direction of the ferromagnet in the magnetization-free layer, for example, and the bit wiring is arranged in parallel to the difficult-magnetization axis of the ferromagnet in the magnetization-free layer.
Then, when data is written into the TMR element, data of “1” or “0” is written into the TMR element in accordance with the direction of the composite magnetic field caused by electric currents that are applied to the bit wiring and writing wiring, respectively. More precisely, the magnetic field due to the writing wiring occurs along the direction of the difficult-magnetization axis of the ferromagnet in the magnetization-free layer and thereby the anti-magnetic property of the ferromagnet in the magnetization-free layer is reduced. At the same time, the magnetic field due to the bit wiring occurs along the direction of the easy-magnetization axis of the ferromagnet in the magnetization-free layer, and data of “1” or “0” is written in accordance with this direction.
On the other hand, when the data written into the TMR element is read out, electric current is applied to the TMR element from the bit wiring and data of “1” or “0” is discriminated depending on a large or small amount of the electric current that flows.
Further, for example, two TMR elements Rs and Rs′ are arranged complementarily, and the FPG can be configured with a readout transistor provided between these two TMR elements Rs and Rs′ and a pass gate transistor (refer to FIG. 4 of Non-patent literature 4).
The bit wirings BL1 and BL2 are arranged respectively corresponding to two TMR elements Rs and Rs′.
Further, when memory data is written, the memory data is written by the magnetic field that the bit wiring and writing wiring generate.
When the memory data written is read out, electric current is made to flow into the TMR element by turning the readout transistor on.
The voltage that corresponds to the external input is applied to one of bit wiring BL1 when the arithmetic operation is performed. The gate voltage of the pass gate transistor changes in accordance with the result of arithmetic operation of the external input and the memory data, and the on/off state of the pass gate transistor changes.
With such configuration, the AND (logical multiply) operation between the external input and the memory data can be performed.
Non-patent literature 1: Kimura, Hanyu & Kameyama “The logic memory VLSI using the ferroelectric device and application” The Institute of Electronics, Information & Communication Engineers, paper magazine, C, Vol. J83-C, No. 8, pp. 749–756, August 2000.
Non-patent literature 2: Kimura, Hanyu, Kameyama, Fujimori, Nakamura & Takasu “The constitution of the logic memory VLSI using the ferroelectric device” Institute of Electronics, Information & Communication Engineers (IEICE), paper magazine, C, Vol. J86-C, No. 8, pp. 886–893, August 2003.
Non-patent literature 3: H. Takasu “Application of the ferroelectric to the logic” FED Review. Vol. 2, No. 7, pp. 1–24, Feb. 24, 2003.
Non-patent literature 4: Kimura, Hanyu & Kameyama “The constitution of the logic memory VLSI using the ferroelectric device” Technical report of IEICE, ICD 2003-5, pp. 749–756, April 2003.